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| NanoAmp Solutions, Inc. 1982 Zanker Road, San Jose, CA 95112 ph: 408-573-8878, FAX: 408-573-8877 www.nanoamp.com NT5DS4M32EG Advance Information 1M x 32 Bits x 4 Banks Double Data Rate Synchronous RAM With Bi-Directional Data Strobe and DLL General Overview The NT5DS4M32EG is 134,217,728 bits of double data rate synchronous dynamic RAM organized as 4 x 1,048,576 bits by 32 I/Os. Synchronous features with Data Strobe allow extremely high performance up to 400Mbps/pin. I/O transactions are possible on both edges of the clock. Range of operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety of high performance memory system applications. Features * VDD = 2.5V5% , VDDQ = 2.5V5% * SSTL_2 compatible inputs/outputs * 4 banks operation * MRS cycle with address key programs * Data I/O transaction on both edges of Data strobe * 4 DQS (1 DQS/Byte) * DLL aligns DQ and DQS transaction with Clock transaction * Edge aligned data & data strobe output * Center aligned data & data strobe input * DM for write masking only * Auto & self refresh * 32ms refresh period (4K cycle) * 144-Ball FBGA package * Maximum clock frequency up to 200MHz * Maximum data rate up to 400Mbps/pin -CAS latency 2,3 (clock) -Burst length (2, 4, 8 and Full page) -Burst type (sequential & interleave) * Full page burst length for sequential burst type only * Start address of the full page burst should be even * All inputs except data & DM are sampled at the rising edge of the system clock * Differential clock input(CK & /CK) Ordering Information Part Number Package Operating Temperature Max. Frequency CL = 3 200MHz 144-Balls Green FBGA 0 - 70 C 200MHz 166MHz CL = 2 111MHz - Max Data Rate 400Mbps/pin 400Mbps/pin 333Mbps/pin Interface NT5DS4M32EG-5G NT5DS4M32EG-5 NT5DS4M32EG-6 SSTL_2 Doc # 14-02-045 Rev A ECN 01-1118 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. 1 NanoAmp Solutions, Inc. Figure 1: PIN CONFIGURATION (Top View) NT5DS4M32EG Advance Information 1 A B C D E F G H J K L M DQS0 DQ4 DQ6 DQ7 DQ17 DQ19 DQS2 DQ21 DQ22 /CAS /RAS /CS 2 DM0 VDDQ DQ5 VDDQ DQ16 DQ18 DM2 DQ20 DQ23 /WE NC NC 3 VSSQ NC VSSQ VDD VDDQ VDDQ NC VDDQ VDDQ VDD NC BA0 4 DQ3 VDDQ VSSQ VSS VSSQ VSSQ VSSQ VSSQ VSSQ VSS BA1 A0 5 DQ2 DQ1 VSSQ VSSQ VSS Thermal VSS Thermal VSS Thermal VSS Thermal VSS A10 A2 A1 6 DQ0 VDDQ VDD VSS VSS Thermal VSS Thermal VSS Thermal VSS Thermal VSS VDD A11 A3 7 DQ31 VDDQ VDD VSS VSS Thermal VSS Thermal VSS Thermal VSS Thermal VSS VDD A9 A4 8 DQ29 DQ30 VSSQ VSSQ VSS Thermal VSS Thermal VSS Thermal VSS Thermal VSS RFU1 A5 A6 9 DQ28 VDDQ VSSQ VSS VSSQ VSSQ VSSQ VSSQ VSSQ VSS RFU2 A7 10 VSSQ NC VSSQ VDD VDDQ VDDQ NC VDDQ VDDQ VDD CK A8/AP 11 DM3 VDDQ DQ26 VDDQ DQ15 DQ13 DM1 DQ11 DQ9 NC /CK CKE 12 DQS3 DQ27 DQ25 DQ24 DQ14 DQ12 DQS1 DQ10 DQ8 NC MCL VREF NOTE: 1. RFU1 is reserved for A12 2. RFU2 is reserved for BA2 3. VSS Thermal balls are optional Table 1: PIN Description CK, /CK CKE /CS /RAS /CAS /WE DQS DM RFU Differential Clock Input Clock Enable Chip Select Row Address Strobe Column Address Strobe Write Enable Data Strobe Data Mask Reserved for Future Use BA0, BA1 A0 ~ A11 DQ0 ~ DQ31 VDD VSS VDDQ VSSQ MCL Bank Select Address Address Input Data Input/Output Power Ground Power for DQ's Ground for DQ's NC Doc # 14-02-045 Rev A ECN 01-1118 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. 2 NanoAmp Solutions, Inc. NT5DS4M32EG Advance Information Table 2: INPUT/OUTPUT FUNCTIONAL DESCRIPTION Symbol CK, /CK# Type Input Function The differential system clock inputs. All of the input are sampled on the rising edge of the clock except DQ's and DM's that are sampled on both edges of the DQS. CKE high activates and CKE low deactivates the internal clock,input buffers and output drivers. By deactivating the clock, CKE low indicates the Power down mode or Self refresh mode. /CS enables(registered Low) and disables(registered High) the command decoder. When /CS is registered High,new commands are ignored but previous operations are continued. Latches row addresses on the positive going edge of the CK with /RAS low. Enables row access & precharge. Latches Column addresses on the positive going edge of the CK with / CAS low. Enables column access. Enables write operation and row precharge. Latches data in starting from / CAS, /WE active. Data inputs and outputs are synchronized with both edge of DQS. DQS0 for DQ0~DQ7, DQS1 for DQ8~DQ15, DQS2 for DQ16~DQ23, DQS3 for DQ24~DQ31 Data-In mask. Data-In is masked by DM Latency=0 when DM is high in burst write. DM0 for DQ0 ~ DQ7, DM1 for DQ8 ~ DQ15, DM2 for DQ16 ~ DQ23, DM3 for DQ24 ~ DQ31. Data inputs and outputs are multiplexed on the same pins. Select which bank is to be active. Row,Column addresses are multiplexed on the same pin. Row address : RA0 ~ RA11, Column address : CA0 ~ CA7. Column address CA8 is used for auto precharge. Power and ground for the input buffers and core logic. Isolated power supply and ground for the output buffers to provide improved noise immunity. Reference voltage for inputs, used for SSTL interface. This pin is recommend to be left "No Connection" on the device. Not internally connected CKE Input /CS /RAS /CAS /WE DQS0 ~ DQS3 Input Input Input Input Input, Output DM0 ~ DM3 DQ0 ~ DQ31 BA0 ~ BA1 A0 ~ A11 VDD, VSS VDDQ, VSSQ VREF NC/RFU MCL Input Input, Output Input Input Power Supply Power Supply Power Supply No Connection/ Reserved for future use Must Connect Low # : The timing reference point for the differential clocking is the cross point of CK and /CK. For any applications using the single ended clocking, apply VREF to /CK pin. Doc # 14-02-045 Rev A ECN 01-1118 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. 3 NanoAmp Solutions, Inc. NT5DS4M32EG Advance Information Figure 2: FUNCTIONAL BLOCK DIAGRAM (1Mbit x 32 I/O x 4 Bank) 32 Input Buffer LWE I/O Control CK, /CK Bank Select Data Input Register Serial to parallel 64 LDMi 1M x 32 2-bit prefetch Output Buffer Sense AMP Refresh Counter Row Buffer 1M x 32 1M x 32 1M x 32 Row Decoder 64 32 x32 DQi CK,/CK Address Register ADDR Column Decoder LRAS LCBR Column Buffer Latency & Burst Length * Strobe Gen. LCKE LRAS LCBR LWE Programming Register DLL LCAS LWCBR LDMi CK,/CK Timing Register CK,/CK CKE /CS /RAS /CAS /WE DMi Doc # 14-02-045 Rev A ECN 01-1118 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. 4 NanoAmp Solutions, Inc. Figure 3: SIMPLIFIED STATE DIAGRAM NT5DS4M32EG Advance Information SELF REFRESH FS RE X FS RE MODE REGISTER SET MRS IDLE CK CK EH REFA A UTO REFRESH EL POWER DOWN CK CK EH EL A CT POWER DOWN ROW A CTIVE BS T WRITE WRITEA REA DA REA D WRITE WRITE WRITEA WRITEA WRITE A PRE REA D REA D REA DA REA DA REA D A POWER A PPLIED POWER ON PRE PRECHA RGE PR E Doc # 14-02-045 Rev A ECN 01-1118 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. E PR Automatic Sequence Command Sequence WRITEA : Write wit h Autoprecharge READA : Read wit h Autoprecharge 5 NanoAmp Solutions, Inc. NT5DS4M32EG Advance Information FUNCTIONAL DESCRIPTION Power-Up Sequence DDR SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. 1. Apply power and keep CKE at low state (All other inputs may be undefined) - Apply VDD before or at the same time as VDDQ. - Apply VDDQ before or at the same time as VREF & VTT 2. Start clock and maintain stable condition for minimum 200s 3. The minimum of 200s after stable power and clock (CK,/CK), apply NOP and CKE to be high. 4. Issue precharge command for all banks of the device. 5. Issue a EMRS command to enable DLL *1 6. Issue a MRS command to reset DLL. The additional 200 clock cycles are required to lock the DLL. 8. Issue at least 2 or more auto-refresh commands. 9. Issue a mode register set command with A8 to low to initialize the mode register. *1 Every "DLL Enable" command resets DLL. Therefore sequence 6 can be skipped during power-up. Instead of it, the additional 200cycles of clock input is required to lock the DLL after enabling DLL. *2 Sequence of 6 & 7 is regardless of the order. *1,2 7. Issue precharge command for all banks of the device. Figure 4: Power-Up & Initialization Sequence /CK CK tRP 2Clock min. MRS DLL Reset 2Clock min. Precharge ALL Banks tRP 1st Auto Refresh tRFC 2nd Auto Refresh tRFC 2Clock min. Mode Register Set Any Command Command Precharge ALL Banks EMRS Input must be stable for 200us 200 Clock min. Doc # 14-02-045 Rev A ECN 01-1118 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. 6 NanoAmp Solutions, Inc. Mode Register Set (MRS) NT5DS4M32EG Advance Information The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs /CAS latency, address mode, burst length, test mode, DLL reset and various vendor specific option to make DDR SDRAM useful for variety of different applications. The default value of the mode register is not defined, therefore the mode register must be written after EMRS setting for proper operation. The mode register is written by asserting low on /CS, /RAS, /CAS and WE (The DDR SDRAM should be in active mode with CKE already high prior to writing into the mode register). The state of address pins A0 ~ A11 and BA0,BA1 in the same cycle as /CS, /RAS, /CAS and /WE going low is written in the mode register. Minimum two clock cycles are requested to complete the write operation in the mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. The mode register is divided into various fields depending on functionality. The burst length uses A0~A2, address mode uses A3, /CAS latency (read latency from column address) uses A4 ~ A6. A7 is used for test mode. A8 is used for DLL for DLL reset. A7, A8, BA0, and BA1 must be set to low for normal MRS operation. Refer to the table for specific codes for various burst length, address modes and /CAS latencies. BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus RFU 0 RFU DLL TM /CAS Latency BT Burst Length Mode Register Burst Type DLL A8 0 1 DLL Reset No Yes Test Mode A7 0 1 Mode Normal Test Burst Length /CAS Latency BA0 0 1 Mode MRS EMRS A6 0 0 0 0 1 * RFU(Reserved for future use) should stay "0" during MRS cycle . 1 1 1 A5 0 0 1 1 0 0 1 1 A4 0 1 0 1 0 1 0 1 Latency Reserved Reserved 2 3 Reserved Reserved Reserved Reserved A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 Burst Type Sequential Reserved 2 4 8 Reserved Reserved Reserved Full page Interleave Reserved 2 4 8 Reserved Reserved Reserved Reserved A3 0 1 Type Sequential Interleave Figure 5: MRS Cycle /CK CK Precharge All Banks Any Command 0 1 2 3 4 5 6 7 8 Command NOP NOP tRP * 2 NOP MRS * 1 NOP tMRD = 2 tCK NOP NOP * 1 : MRS can be issued only at all banks precharge state. * 2 : Minium tRP is required to issue MRS command. Doc # 14-02-045 Rev A ECN 01-1118 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. 7 NanoAmp Solutions, Inc. Extended Mode Register Set (EMRS) NT5DS4M32EG Advance Information The extended mode register stores the data for enabling or disabling DLL and selecting output driver strength. The default value of the extended mode register is not defined, therefore the extended mode register must be written after power up for enabling or disabling DLL. The extended mode register is written by asserting low on /CS, /RAS, /CAS, / WE and high on BA0 (The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register). The state of address pins A0,A2~A5, A7~A11 and BA1 in the same cycle as /CS,/RAS,/CAS and /WE going low are written in the extended mode register. A1and A6 are used for setting driver strength to weak or matched impedance. Two clock cycles are required to complete the write operation in the extended mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state A0 is used for DLL enable or disable."High"on BA0 is used for EMRS. All the other address pins except A0,A1, A6 and BA0 must be set to low for proper EMRS operation. Refer to the table for specific codes. BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus RFU 1 RFU DIC RFU DIC DLL Extended Mode Register BA0 0 1 Mode MRS EMRS A6 0 1 A1 1 1 Output Driver Impedance Control Weak Matched impedance 60% of full drive strength 30% of full drive strength A0 0 1 DLL Enable Enable Disable * RFU(Reserved for Future Use) should stay "0" during MRS cycle. Figure 6: LOW Frequency Operation Mode DLL DISABLE MODE /CK CK tRP 2Clock min. 2Clock min. DLL Disable Mode tRP 2Clock min. 2Clock min. 2Clock min. Command Precharge ALL Banks EMRS MRS*1 CMD Precharge ALL Banks EMRS MRS DLL RESET MRS Active Read*2 Enter DLL Disable Mode CL=2/3 BL=FREE Exit DLL Disable Mode 200 Clock min. Notes: - DLL disable mode is operating mode for low operating frequency between 143MHz and 83MHz without DLL. - This DLL disable mode is useful for power saving. - All banks precharge or a bank precharge command can omit before entering and exiting DLL disable mode. *1 : CL=2 & 3 and BL can set any burst length at DLL disable mode. *2 : A Read command can be applied as far as tRCD is satisfied after any bank active command. And it needs an additional 200 clock cycles for read operation after exiting DLL disable mode. Doc # 14-02-045 Rev A ECN 01-1118 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. 8 NanoAmp Solutions, Inc. Burst Mode Operation NT5DS4M32EG Advance Information Burst mode operation is used to provide a constant flow of data to memory location (write cycle), or from memory location (read cycle). There are two parameters that define how the burst mode operates. These parameters including burst sequence and burst length are programmable and determined by address A0 ~ A3 during the Mode Register Set command. The burst type is used to define the sequence in which the burst data will be delivered or stored to the DDR SDRAM. Two types of burst sequences are supported, sequential and interleaved. See the below table. The burst length controls the number of bits that will be output after a read command, or the number of bits to be input after a write command. The burst length can be programmed to have values of 2,4,8 or full page. For the full page operation, the starting address must be an even number and the burst stop at the end of burst. Table 3: Burst Length and Sequence Burst Length 2 Starting Address (A2, A1, A0) xx0 xx1 x00 4 x01 x10 x11 000 001 010 8 011 100 101 110 111 Full Page (256) n = A0 - A7, A0 = 0 Sequential Mode 0-1 1-0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 Cn, Cn+1, Cn+2, ..., Cn-1 Interleave Mode 0-1 1-0 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-0-1-2-3 7-6-5-4-3-2-1-0 Not supported Bank Activation Command The Bank Activation command is issued by holding /CAS and /WE high with /CS and /RAS low at the rising edge of the clock. The DDR SDRAM has four independent Banks, so two Bank Select Addresses(BA0, BA1) are supported. The Bank Activation command must be applied before any Read or Write operation is executed.The delay from the Bank Activation command to the first read or write command must meet or exceed the minimum of /RAS to /CAS delay time (tRCDR/tRCDW min). Once a bank has been activated, it must be precharged before another Bank Activation command can be applied to the same bank. The minimum time interval between interleaved Bank Activation commands(Bank A to B and vice versa) is the Bank to Bank delay time (tRRD min). Figure 7: Bank Activation Command Cycle (/CAS Latency = 3) 0 /CK CK Address Bank A Row Addr. Bank A Col. Addr. Bank A Row Addr. Bank B Row Addr. 1 2 n n+1 n+2 /RAS-/CAS delay time (tRCDR for READ) Bank A Activate READ A wit h Auto Precharge /RAS-/RAS delay time (tRRD) Bank A Activate Bank B Activate : Don't care Command NOP NOP NOP Row cycle Time (tRC) Doc # 14-02-045 Rev A ECN 01-1118 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. 9 NanoAmp Solutions, Inc. Burst Read Operation NT5DS4M32EG Advance Information Burst Read operation in DDR SDRAM is in the same manner as the current SDRAM such that the burst read command is issued by asserting /CS and /CAS low while holding /RAS and /WE high at the rising edge of the clock after tRCD from the bank activation. The address inputs (A0~A7) determine the starting address for the Burst. The Mode Register sets type of burst (Sequential or interleave) and burst length(2,4,8, Full page). The first output data is available after the /CAS Latency from the READ command, and the consecutive data are presented on the falling and rising edge of Data Strobe adopted by DDR SDRAM until the burst length is completed. Figure 8: Burst Read (Burst Length = 4, /CAS Latency = 3) 0 /CK CK Command DQS /CAS Latency = 3 DQ's Dout 0 Dout 1 Dout 2 Dout 3 1 2 3 4 5 6 7 8 READ NOP NOP tRPRE NOP NOP NOP tRPST NOP NOP NOP Burst Write Operation The Burst Write command is issued by having /CS, /CAS and /WE low while holding /RAS high at the rising edge of the clock. The address inputs determine the starting column address. There is no real write latency required for burst write cycle. The first data for burst write cycle must be applied at the first rising edge of the data strobe enabled after tDQSS from the rising edge of the clock that the write command is issued.The remaining data inputs must be supplied on each subsequent falling and rising edge of Data Strobe until the burst length is completed. When the burst has been finished, any additional data supplied to the DQ pins will be ignored. Figure 9: Burst Write (Burst Length = 4) 0 /CK CK Command NOP WRITEA NOP WRITEB NOP NOP NOP tWPST NOP NOP 1 2 3 4 5 6 7 8 DQS DQ's tDQSSmax tWPREH tWPRES Din a0 Din a1 Din a 2 Din a3 Din b0 Din b1 Din b2 Din b3 Doc # 14-02-045 Rev A ECN 01-1118 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. 10 NanoAmp Solutions, Inc. Burst Interruption Read Interrupted by Read NT5DS4M32EG Advance Information Burst Read can be interrupted before completion of the burst by new Read command of any bank. When the previous burst is interrupted, the remaining address are overridden by the new address with the full burst length. The data from the previous Read command continues to appear on the outputs until the /CAS latency from the interrupting Read command is satisfied. Read to Read interval is minimum 1 tCK. Figure 10: Burst Interrupted by Read (Burst length = 4, /CAS Latency = 3) 0 /CK CK Command READ A READ B NOP NOP NOP NOP NOP NOP NOP 1 2 3 4 5 6 7 8 DQS /CAS Latency = 3 DQ's Douta0 Douta1 Doutb0 Doutb1 Doutb2 Doutb3 Read Interrupted by Burst stop & Write To interrupt Burst Read with a write command, Burst stop command must be asserted to avoid data contention on the I/O bus by placing the DQ's(Output drivers) in a high impedance state at least one clock cycle before the Write Command is initiated. Once the burst stop command has been issued, the minimum delay to a write command is CL(RU). [CL is /CAS Latency and RU means round up to the nearest integer.] Figure 11: Burst Interrupted by Burst Stop & Write (Burst Length = 4, /CAS Latency = 3) 0 /CK CK Command DQS /CAS Latency = 3 DQ's READ Burst stop NOP tRPRE Preamble Dout0 Dout1 1 2 3 4 5 6 7 8 NOP NOP WRITE NOP NOP tDQSS tWPREH tWPRES Din 0 Din 1 Din 2 Din 3 Doc # 14-02-045 Rev A ECN 01-1118 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. 11 NanoAmp Solutions, Inc. Read Interrupted by Precharge NT5DS4M32EG Advance Information Burst Read can be interrupted by precharge of the same bank. The minimum 1 clock cycle is required for the read precharge interval. Precharge command to output disable latency is equivalent to the /CAS latency. Figure 12: Burst Interrupted by Precharge (Burst Length = 8, /CAS Latency = 3) 0 /CK CK 1tCK 1 2 3 4 5 6 7 8 Command READ Precharge NOP NOP NOP tRPST NOP NOP NOP NOP DQS /CAS Latency = 3 DQ's tRPRE Dout 0 Dout 1 Dout 2 Dout 3 Dout 4 Dout 5 Dout 6 Dout 7 Interrupted by precharge Write Interrupted by Write Burst Write can be interrupted by the new Write Command before completion of the previous burst write, with the only restriction being that the interval that separates the commands must be at least one clock cycle. When the previous burst is interrupted, the remaining addresses are overridden by the new addresses and data will be written into the device until the programmed burst length is satisfied. Figure 13: Write Interrupted by Write (Burst Length = 4) 0 /CK CK 1tCK 1 2 3 4 5 6 7 8 Command NOP WRITEA WRITEB tWPREH NOP NOP NOP NOP NOP NOP DQS /CAS Latency = 3 DQ's tWPRES Din a0 Din a1 Din b0 Din b1 Din b2 Din b3 Doc # 14-02-045 Rev A ECN 01-1118 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. 12 NanoAmp Solutions, Inc. Write Interrupted by Read & DM NT5DS4M32EG Advance Information A burst write can be interrupted by a read command of any bank. The DQ's must be in the high impedance state at least one clock cycle before the interrupting read data appear on the outputs to avoid data contention. When the read command is registered, any residual data from the burst write cycle must be masked by DM. The delay from the last data to read command (tWTR) is required to avoid the data contention DRAM inside. Data that are presented on the DQ pins before the read command is initiated will actually be written to the memory. Read command interrupting write can not be issued at the next clock edge of the write command. Figure 14: Write Interrupted by Read & DM (Burst Length = 8) 0 /CK CK 1 2 3 4 5 6 7 8 Command WRITE NOP tDQSSmax NOP NOP NOP tWTR READ NOP NOP NOP DQS /CAS Latency=3 DQ's tWPRES Din 0 Din 1 Din 2 Din 3 Din 4 Din 5 Din 6 Din 7 Dout0 Dout1 DM tDQSSmin tWTR DQS /CAS Latency=3 DQ's tWPRES Din 0 Din 1 Din 2 Din 3 Din 4 Din 5 Din 6 Din 7 Dout0 Dout1 DM Doc # 14-02-045 Rev A ECN 01-1118 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. 13 NanoAmp Solutions, Inc. Write Interrupted by Precharge & DM NT5DS4M32EG Advance Information A burst Write can be interrupted by a precharge of the same bank before completion of the previous burst. A write recovery time (tWR) is required from the last data to precharge command. When Precharge command is asserted, any residual data from the burst write cycle must be masked by DM. Figure 15: Write Interrupted by Precharge & DM 0 /CK CK 1 2 3 4 5 6 7 8 Command NOP WRITE A NOP NOP NOP tWR NOP Precharge WRITE B NOP tDQSSmax tDQSSmax tWPREH DQS tWPREH tWPRES tWPRES Din a 0 Din a 1 Max tDQ SS DQ's Din a0 Din a1 Din a2 Din a 3 Din a4 Din a 5 Din a 6 Din a 7 DM tDQSSmin tWR tDQSSmin tWPREH tWPRES Din b0 Din b1 Din b2 DQS tWPREH tWPRES Min tDQSS DQ's Din a0 Din a1 Din a2 Din a3 Din a4 Din a5 Din a6 Din a 7 DM Doc # 14-02-045 Rev A ECN 01-1118 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. 14 NanoAmp Solutions, Inc. BURST STOP COMMAND NT5DS4M32EG Advance Information The Burst stop command is initiated by having /RAS and /CAS high with /CS and /WE low at the rising edge of the clock only. The Burst Stop command has the fewest restrictions making it the easiest method to use when terminating a burst operation before it has been completed. When the Burst Stop command is issued during a burst read cycle, both the data and DQS(Data Strobe) go to a high impedance state after a delay which is equal to the /CAS Latency set in the Mode Register. The Burst Stop command, however, is not supported during a write burst operation. Figure 16: Burst Stop Command (Burst Length = 4, /CAS Latency = 3) 0 /CK CK 1tCK Burst Stop 1 2 3 4 5 6 7 8 Command READ NOP NOP NOP NOP NOP NOP NOP DQS /CAS Latency = 3 DQ's Dout 0 Dout 1 The burst ends after a delay equal to the /CAS Latency DM FUNCTION The DDR SDRAM has a Data mask function that can be used in conjunction with data Write cycle only, not Read cycle. When the Data Mask is activated (DM high) during write operation, the write data is masked immediately (DM to Data-mask Latency is Zero). DM must be issued at the rising edge or the falling edge of Data Strobe instead of a clock edge. Figure 17: DM Function (Burst Length = 8) 0 1 2 3 4 5 6 7 8 /CK CK Command DQS DQ's DMM D WRITE tDQSS NOP NOP NOP NOP NOP NOP NOP NOP tWPREH tWPRES Din 0 Din 1 Din 2 Din 3 Din 4 Din 5 Din 6 Din 7 Mask ed by DM=H Doc # 14-02-045 Rev A ECN 01-1118 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. 15 NanoAmp Solutions, Inc. AUTO-PRECHARGE OPERATION NT5DS4M32EG Advance Information The Auto precharge command can be issued by having column address A8 High when a Read or a Write command is asserted into the DDR SDRAM. If A8 is low when Read or Write command is issued, normal Read or Write burst operation is asserted and the bank remains active after the completion of the burst sequence. When the Auto precharge command is activated, the active bank automatically begins to precharge at the earliest possible moment during read or write cycle after tRAS (min) is satisfied. Read with Auto Precharge If a Read with Auto-precharge command is initiated, the DDR SDRAM automatically starts the precharge operation on 2 clock previous to the end of burst from a Read with Auto-Precharge command when tRAS (min) is satisfied. If not, the start point of precharge operation will be delayed until tRAS (min) is satisfied. The bank started the Precharge operation once cannot be reactivated and the new command can not be asserted until the Precharge time (tRP) is satisfied. Figure 18: Read With Auto Precharge (Burst Length = 4, /CAS Latency = 3) 0 /CK CK 1 2 3 4 5 6 7 8 Command BANK A ACTIVE NOP NOP READ A Auto Prec har ge NOP NOP NOP NOP NOP tRCDR (min) tRAS (min) DQS /CAS Latency = 3 DQ's Douta0 Douta1 Douta2 Douta3 tRP * Bank can be reactiv ated at completion of tRP Auto-Precharge start point tRC(min) When the Read with Auto Precharge command is issued, new command can be asserted at T5, T6 and T7 respectively as follows. Asserted Command READ READ + AP ACTIVE PRECHARGE AP = Auto Precharge For Same Bank T5 READ (no AP) READ + AP Illegal Legal T6 READ (no AP) READ + AP Illegal Legal T7 Illegal Illegal Illegal Illegal T5 Legal Legal Legal Legal For Different Bank T6 Legal Legal Legal Legal T7 Legal Legal Legal Legal Doc # 14-02-045 Rev A ECN 01-1118 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. 16 NanoAmp Solutions, Inc. Write with Auto Precharge NT5DS4M32EG Advance Information If A8 is high when Write command is issued, the write with Auto-Precharge function is performed. Any new command to the same bank should not be issued until the internal precharge is completed. The internal precharge begins after keeping tWR (min). Figure 19: Write with Auto Precharge (Burst Length = 4, /CAS Latency = 3) 0 /CK CK WRITE A Auto Prec har ge 1 2 3 4 5 6 7 8 Command BANK A ACTIVE NOP NOP NOP NOP NOP NOP NOP t WPREH DQS /CAS Latency = 3 DQ's t WPRES Din a0 Din a1 Din a 2 Din a 3 * Bank can be reactiv ated at completion of t RP t WR t tRP Internal precharge starts Asserted Command WRITE WRITE + AP READ READ + AP Active Precharge For Same Bank 3 Write No AP Write + AP Illegal For Different Bank 7 Illegal Illegal READ No AP READ + AP Illegal Illegal 4 Write No AP Write + AP READ No AP + DM READ + AP + DM Illegal Illegal 5 Write No AP Write + AP READ No AP + DM READ + AP + DM Illegal Illegal 6 Illegal Illegal READ No AP READ + AP Illegal Illegal 8 Illegal Illegal 3 Legal Legal 4 Legal Legal 5 Legal Legal 6 Legal Legal 7 Legal Legal Illegal Illegal Illegal Illegal Legal Legal Illegal Illegal Illegal Illegal Illegal Illegal Illegal Legal Legal Illegal Legal Legal Illegal Legal Legal Legal Legal Legal Legal Legal Legal AP = Auto Precharge DM : Refer to "Write Interrupted by Read & DM" Doc # 14-02-045 Rev A ECN 01-1118 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. 17 NanoAmp Solutions, Inc. PRECHARGE COMMAND NT5DS4M32EG Advance Information The precharge command is issued when /CS, /RAS, and /WE are low and /CAS is high at the rising edge of the clock, CK. The precharge command can be used to precharge each bank respectively or all banks simultaneously. The Bank select addresses(BA0, BA1) are used to define which bank is precharged when the command is initiated. For write cycle, tWR (min). must be satisfied from the start of the last burst write cycle until the precharge command can be issued. After tRP from the precharge, an active command to the same bank can be initiated. Table 4: Bank Selection for Precharge by Bank Address Bits A8/AP 0 0 0 0 1 BA1 0 0 1 1 X BA0 0 1 0 1 X Precharge Bank A Only Bank B Only Bank C Only Bank D Only All Banks AUTO REFRESH An Auto Refresh command is issued by having /CS, /RAS and /CAS held low with CKE and /WE high at the rising edge of the clock, CK. All banks must be precharged and idle for a tRP (min) before the Auto Refresh command is applied. The refresh addressing is generated by the internal refresh address counter. This makes the address bits "Don't care" during an Auto Refresh command. When the refresh cycle has completed, all banks will be in the idle state. A delay between the Auto Refresh command and the next Activate Command or subsequent Auto Refresh Command must be greater than or equal to the tRFC (min). Figure 20: Auto Refresh 0 /CK CK Command CKE=High Auto Refresh 1 2 3 4 5 6 7 8 9 10 11 PRE All Banks CMD tRP tRFC Doc # 14-02-045 Rev A ECN 01-1118 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. 18 NanoAmp Solutions, Inc. SELF REFRESH NT5DS4M32EG Advance Information A self refresh command is defined by having /CS, /RAS, /CAS and CKE low with /WE high at the rising edge of the clock (CK). Once the self refresh command is initiated, CKE must be held low to keep the device in self refresh mode. During the self refresh operation, all inputs except CKE are ignored. The clock is internally disabled during self refresh operation to reduce power consumption. The self refresh is exited by supplying stable clock input before returning CKE high, asserting deselect or NOP command and then asserting CKE high for longer than tXSR for locking of DLL. Figure 21: Self Refresh /CK CK Command CKE Self PRE Refresh All Banks Self Refresh Active Read tIS tXSA *1 tXSR *2 *1 Exit self refresh to bank active command, a write command can be applied as far as tRCD is satisfied after any bank active command. *2 Exit self refresh to read command. POWER DOWN MODE The power down is entered when CKE Low, and exited when CKE High. Once the power down mode is initiated, all of the receiver circuits except CK and CKE are gated off to reduce power consumption. All banks should be in idle state prior to entering the precharge power down mode and CKE should be set high at least 1tCK+tIS prior to Row active command. During power down mode, refresh operations cannot be performed, therefore the device cannot remain in power down mode longer than the refresh period (tREF) of the device. Figure 22: Power Down Mode 0 /CK CK Command Precharge pow er dow n Entry Precharge pow er dow n Exit Active pow er dow n Entry Active pow er dow n Exit 1 2 3 4 5 6 7 8 9 10 11 12 13 Precharge Active Read NOP NOP CKE tIS tIS tPDEX tIS tIS Doc # 14-02-045 Rev A ECN 01-1118 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. 19 NanoAmp Solutions, Inc. NT5DS4M32EG Advance Information Table 5: Absolute Maximum Ratings Parameter Voltage on any pin relative to Vss Voltage on VDD supply relative to Vss Voltage on VDDQ supply relative to Vss Storage Temperature Power Dissipation Short circuit current Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATING are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. Symbol VIN, VOUT VDD VDDQ TSTG PD IOS Value -0.5~3.6 -1.0~3.6 -0.5~3.6 -55~150 2.0 50 Unit V V V C W mA Table 6: Power & DC Operating Condition (SSTL_2 In/Out) Recommended operating conditions (Voltage referenced to Vss, TA = 0 to 70C Parameter Device Supply Voltage Output Supply Voltage Reference Voltage Termination Voltage Input Logic High Voltage Input Logic Low Voltage Output Logic High Current Output Logic Low Current Input Leakage Current Output Leakage Current Note : 1. VDD / VDDQ = 2.5V 5% / 2.5V 5% 2. VREF is expected to equal 0.50* VDDQ of the transmitting device and to track variations in the DC level of the same. Peak to peak noise on the VREF may not exceed 2% of the DC value. Thus, from 0.50* VDDQ, VREF is allowed 25mV for DC error and an additional 25mV for AC noise. 3. Vtt of the transmitting device must track VREF of the receiving device. 4. VIH(max.) = VDDQ +1.5V for a pulse and it which can not be greater than 1/3 of the cycle rate. 5. VIL(mim.) =-1.5V for a pulse width and it can not be greater than 1/3 of the cycle rate. 6. For any pin under test input of 0V VIN VDD is acceptable. For all other pins that are not under test VIN = 0V. 7. VOH (Output logic high voltage) min = Vtt (min) + 0.76 8. VOL (Output logic low voltage) max = Vtt (max) - 0.76 9. DQs are disabled; 0V VOUT VDDQ Symbol VDD VDDQ VREF Vtt VIH VIL IOH IOL IIL IOL Min 2.375 2.375 0.49*VDDQ VREF-0.04 VREF+0.15 -0.30 -15.2 15.2 -5 -5 Typ 2.50 2.50 -VREF ------- Max 2.625 2.625 0.51*VDDQ VREF+0.04 VDDQ+0.30 VREF-0.15 --5 5 Unit V V V V V V mA mA uA uA Note 1 1 2 3 4 5 7 8 6 9 Doc # 14-02-045 Rev A ECN 01-1118 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. 20 NanoAmp Solutions, Inc. NT5DS4M32EG Advance Information Table 7: DC Characteristic Recommended operating conditions (Voltage Reference to Vss=0V, VDD/VDDQ=2.5V5%/2.5V5%, TA= 0 to 70C) Parameter Operating Current (One Bank Active) Precharge Standby Current in Power Down Mode Precharge Standby Current in Non Power Down Mode Active Standby Current in Power Down Mode Active Standby Current in non Power Down Mode Operating Current (Burst Mode) Refresh Current Self Refresh Current Operating Current (4Bank Interleaving) Note: 1. Measured with outputs open. 2. Refresh period is 32ms. Symbol ICC1 ICC2P Test Condition Burst Length=2, tRCtRC(min) IOL=0mA, tCK=tCK(min) CKEVIL(max), tCK=tCK(min) CKEVIH(min), /CSVIH(min) tCK=tCK(min) CKEVIL(max), tCK=tCK(min) CKEVIH(min), /CSVIH(min) tCK=tCK(min) IOL=0mA, tCK=tCK(min), Page Burst, All Banks Activated tRCtRFC(min) CKE0.2V Burst Length=4, tRCtRC(min) IOL=0mA, tCK=tCK(min) All 160 15 Unit mA mA Note 1 ICC2N 40 mA ICC3P 17 mA ICC3N ICC4 ICC5 ICC6 ICC7 70 420 200 6 560 mA mA mA mA mA 2 Table 8: AC INPUT OPERATING CONDITIONS Recommended operating conditions (Voltage Reference to Vss=0V, VDD/VDDQ=2.5V5%/2.5V5%, TA= 0 to 70C) Parameter Input High (Logic1) Voltage : DQ Input Low (Logic0) Voltage: DQ Clock Input Differential Voltage; CK and /CK Clock Input Crossing Point Voltage; CK and /CK Note : Symbol VIH VIL VID VIX Min VREF+0.35 -0.7 0.5*VDDQ-0.2 Typ ----- Max -VREF-0.35 VDDQ+0.6 0.5*VDDQ+0.2 Unit V V V V Note 1 2 1. VID is the magnitude of the difference between the input level on CK and the input level on /CK 2. The value of VIX is expected to equal 0.5* VDDQ of the transmitting device and must track variation in the DC level of the same Doc # 14-02-045 Rev A ECN 01-1118 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. 21 NanoAmp Solutions, Inc. NT5DS4M32EG Advance Information Table 9: AC Operating Test Conditions (VDD = 2.5V0.125V, TA=0 to 70C) Parameter Input Reference voltage for CK (for signal ended) CK and /CK signal maximum peak swing CK signal minimum slew rate Input levels(VIH/VIL) Input timing measurement reference level Output timing measurement reference level Output load condition Value 0.50*VDDQ 1.5 1.0 VREF+0.35/VREF-0.35 VREF Vtt See Figure 23 Unit V V V/ns V V V Note Figure 23: Output Load Circuit Vtt=0.5*V DDQ O RT=50 Output O Z0=50 n V REF =0.5*V DDQ CLOAD=20pF Table 10: Capacitance (VDD = 2.5V, TA = 25C, f = 1MHz) Parameter Input Capacitance (CK, /CK) Input Capacitance (A0~A11, BA0~BA1) Input Capacitance (CKE, /CS, /RAS, /CAS, /WE) Data & DQS input/output capacitance (DQ0~DQ31) Input Capacitance (DM0~DM3) Symbol CIN1 CIN2 CIN3 COUT CIN4 Min 2.0 2.0 2.0 4.0 4.0 Max 3.0 3.0 3.0 5.0 5.0 Unit pF pF pF pF pF Table 11: Decoupling Capacitance Guide Line (Recommended decoupling capacitance added to power line at board) Parameter Decoupling Capacitance between VDD and VSS Decoupling Cpaacitance between VDDQ and VSSQ Note : 1. VDD and VDDQ pins are separated from each other. Symbol CDC1 CDC2 Value 0.1+0.01 0.1+0.01 Unit F F All VDD pins are connected internally on-chip. All VDDQ pins are connected internally on-chip. 2. VSS and VSSQ pins are separated each other. All VSS pins are connected internally on-chip. All VSSQ pins are connected internally on-chip. Doc # 14-02-045 Rev A ECN 01-1118 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. 22 NanoAmp Solutions, Inc. . NT5DS4M32EG Advance Information Table 12: AC Characteristics Parameter CK cycle time CK high level width CK low level width DQS out access time from CK Output Access time from CK Data Strobe edge to Dout edge Read preamble Read postamble CK to Valid DQS-in DQS-in setup time DQS-in hold time DQS write postamble DQS-in high level width DQS-in low level width Address and Control input setup Address and Control input hold DQ and DM setup time to DQS DQ and DM hold time to DQS CL=3 CL=2 tCH tCL tDQSCK tAC tDQSQ tRPRE tRPST tDQSS tWPRES tWPREH tWPST tDQSH tDQSL tIS tIH tDS tDH tHP Symbol -5G Min 5.0 9.0 0.45 0.45 -0.7 -0.7 -0.9 0.4 0.8 0 0.3 0.4 0.4 0.4 1.0 1.0 0.45 0.45 tCLMIN -5 Max 12 12 0.55 0.55 +0.7 +0.7 0.45 1.1 0.6 1.2 --0.6 0.6 0.6 ----Min 5.0 -0.45 0.45 -0.7 -0.7 -0.9 0.4 0.8 0 0.3 0.4 0.4 0.4 1.0 1.0 0.45 0.45 tCLMIN -6 Max 12 -0.55 0.55 +0.7 +0.7 0.45 1.1 0.6 1.2 --0.6 0.6 0.6 ----Min 6.0 -0.45 0.45 -0.7 -0.7 -0.9 0.4 0.8 0 0.3 0.4 0.4 0.4 1.0 1.0 0.45 0.45 tCLMIN Max 12 -0.55 0.55 +0.7 +0.7 0.45 1.1 0.6 1.2 --0.6 0.6 0.6 ----- Unit ns ns tCK tCK ns ns ns tCK tCK tCK ns tCK tCK tCK tCK ns ns ns ns Note 2,3 2,3 1 Clock half period or tCHMIN -- or tCHMIN -- or tCHMIN -- ns 1 Data output hold time from DQS Note 1: tQH tHP -0.45 -- tHP -0.45 -- tHP -0.45 -- ns 1 -. The JEDEC DDR specification currently defines the output data valid window (tDV) as the period when the data strobe and all data associated with that data strobe are coincidentally valid. -. The previously used definition of tDV(=0.35tDK) artificially penalizes system timing budgets by assuming the worst case output valid window even then the clock duty cycle applied to the device is better than 45/55% -. A new AC timing term, tQH which stands for data output hold time from DQS is defined to account for clock duty cycle variation and replaces tDV - tQHmin = tHP-X where . tHP=Minimum half clock period for any given cycle and is defined by clock high or clock low time (tCH, tCL). .X=A frequency dependent timing allowance account for tDQSQmax Note 2 -. For Low frequency operation without DLL (143MHz~83MHz) in CL2/3, need set DLL disable mode for power saving. -. AC parameters for DLL Disable Mode : Same as "-50" AC parameters except tCK. Note 3 -. Under set DLL disable mode by EMRS, -. The tDQSCK can be 0.0ns in 100MHz operation. -. The tDQSCK can be +3.0ns in 143MHz operation. -. The tDQSCK can be -2.0ns in 83MHz operation. Doc # 14-02-045 Rev A ECN 01-1118 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. 23 NanoAmp Solutions, Inc. NT5DS4M32EG Advance Information Table 13: AC Characteristics (cont) Parameter Row cycle time Refresh cycle time Row active time /RAS to /CAS delay to read /RAS to /CAS delay to write Row precharge time Row active to Row active Last data in to Row Precharge Last data in to Row Precharge (Auto Precharge) Internal Write in to Read Col. address to Col. address Mode reigister set cycle time Auto precharge write recovery + precharge Exit self refresh to active command Exit self refresh to read command Power down exit time Refresh interval time Note 1 1. For normal write operation, even numbers of Din are to be written inside DRAM -. AC parameters for DLL Disable Mode(143MHz ~ 83MHz, CL2/3 Only) Symbol -5G Min 60 70 40 18 10 18 2 2 2 2 1 2 6 75 200 1tCK +tIS 7.8 -5 Min 60 70 40 18 10 18 2 2 2 2 1 2 6 75 200 1tCK +tIS 7.8 -6 Max --100k --------------- Max --100k --------------- Min 60 70 40 18 10 18 2 2 2 2 1 2 6 75 200 1tCK +tIS 7.8 Max --100k --------------- Unit ns ns ns ns ns ns tCK tCK tCK tCK tCK tCK tCK ns tCK ns us Note tRC tRFC tRAS tRCDR tRCDW tRP tRRD tWR tWR_A tWTR tCCD tMRD tDAL tXSA tXSR tPDEX tREF 1 1 1 Doc # 14-02-045 Rev A ECN 01-1118 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. 24 NanoAmp Solutions, Inc. NT5DS4M32EG Advance Information Table 14: Simplified Truth Table Command Extended mode register Mode Register Set Auto Refresh Refresh Self Refresh Entry Exit CKEn-1 H H H L H CKEn X X H L H X /CS L L L L H L /RAS L L L H X L /CAS L L L H X H /WE L L H H X H DM X X X X X V BA0,1 A8/AP OP CODE 1,2 OP CODE X X Row Address L H X L H L H X V H L H X L H L L X V H H Bank Selection X X L L H L H H L L X X V L X Column Address 4 4 4 4,6 7 X 3 3 3 3 A11~A9, A7~A0 Note Register Bank Active & Row Address Read & Col Addr. Write & Col Addr. Burst Stop Precharge Auto Precharge Disable Auto Precharge Enable Auto Precharge Disable Auto Precharge Enable Column Address All Banks Entry Exit Entry Exit H X H X 5 Active Power Down H L H L H H L H L H H L X H L H L H L X V X X H X H X X H X V X X H X H X H X V X X H X H X H X X X Precharge Power Down Mode DM X X V X X X 8 No Operation Command X Note 1. OP CODE : Operand Code. A0 ~ A11 & BA0 ~ BA1 : Program Keys. (@EMRS/MRS) 2. EMRS/MRS can be issued only at all banks precharge state. A new command can be issued after 2 clock cycle of EMRS/MRS 3. Auto refresh function are as same as CBR refresh of DRAM. The automatic precharge without row precharge command is meant by "Auto". Auto/Self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected. If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. 5. If A8/AP is "high" at row precharge ,BA0 and BA1 are ignored and all banks are selected. 6. During burst write with auto precharge, new read/write command cannot be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 7. Burst stop command is valid at every burst length. 8. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges(Write DM latency is 0). Doc # 14-02-045 Rev A ECN 01-1118 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. 25 NanoAmp Solutions, Inc. NT5DS4M32EG Advance Information Table 15: Function Truth Table Current State /CS H L L L IDLE L L L L H L L L ROW ACTIVE L L L L L H L L L READ L L L L L H L L L L WRITE L L L L L L L L H H L L H L H L BA, RA BA, A8 X Op-Code, Mode-Add ACT PRE/PREA REFA MRS /RAS X H H H L L L L X H H H H L L L L X H H H H L L L L X H H H H /CAS X H H L H H L L X H H L L H H L L X H H L L H H L L X H H L L /WE X H L X H L H L X H L H L H L H L X H L H L H L H L X H L H L X X X BA0, CA, A8 BA, RA BA, A8 X Op-Code, Mode -Add X X X BA, CA, A8 BA, CA, A8 BA, RA BA, A8 X Op-Code, Mode-Add X X X BA, CA, A8 BA, CA, A8 BA, RA BA, A8 X Op-Code, Mode-Add X X X BA, CA, A8 BA, CA, A8 Address Command DESEL NOP TERM READ/WRITE ACT PRE/PREA REFA MRS DESEL NOP TERM READ/READA WRITE/WRITEA ACT PRE/PREA REFA MRS DESEL NOP TERM READ/READA WRITE/WRITEA ACT PRE/PREA REFA MRS DESEL NOP TERM READ/READA WRITE/WRITEA NOP NOP NOP ILLEGAL*2 Bank Active, Latch RA NOP*4 AUTO-Refresh*5 Mode Register Set*5 NOP NOP NOP Begin Read, Latch CA, Determine Auto-Precharge Begin Write, Latch CA, Determine Auto-Precharge ILLEGAL*2 Precharge/Precharge All ILLEGAL ILLEGAL NOP(Continue Burst to END) NOP(Continue Burst to END) Terminate Burst Terminate Burst, Latch CA, Begin New Read, Determine Auto-Precharge*3 ILLEGAL ILLEGAL*2 Terminate Burst, Precharge ILLEGAL ILLEGAL NOP (Continue Burst to END) NOP (Continue Burst to END) ILLEGAL ILLEGAL Terminate Burst, Latch CA, Begin new Write, Determine Precharge*3 ILLEGAL*2 Terminate Burst with DM-high Precharge ILLEGAL ILLEGAL Action Doc # 14-02-045 Rev A ECN 01-1118 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. 26 NanoAmp Solutions, Inc. Table 15: Function Truth Table Current State /CS H L L READ with AUTO PRECHARGE L L L L L H L L /RAS X H H H L L L L X H H H L L L L X H H H L L L L X H H H L L L L X H H H H L L L L /CAS X H H L H H L L X H H L H H L L X H H L H H L L X H H L H H L L X H H L L H L L L /WE X H L X H L H L X H L X H L H L X H L X H L H L X H L X H L H L X H L H L H H L L X X X BA, RA, A8 BA, RA BA, A8 X Op-Code, Mode-Add X X X BA, CA, A8 BA, RA BA, A8 X Op-Code, Mode-Add X X X BA, CA, A8 BA, RA BA, A8 X Op-Code, Mode-Add X X X BA, CA, A8 BA, RA BA, A8 X Op-Code, Mode-Add X X X BA, CA, A8 BA, CA, A8 BA, RA BA, A8 X Op-Code, Mode-Add Address Command DESEL NOP TERM READ/WRITE ACT PRE/PREA REFA MRS DESEL NOP TERM READ/WRITE ACT PRE/PREA REFA MRS DESEL NOP TERM READ/WRITE ACT PRE/PREA REFA MRS DESEL NOP TERM READ/WRITE ACT PRE/PREA REFA MRS DESEL NOP TERM READ WRITE/WRITEA ACT PRE/PREA REFA MRS NT5DS4M32EG Advance Information Action NOP(Continue Burst to END) NOP(Continue Burst to END) ILLEGAL ILLEGAL*2 ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL NOP(Continue Burst to END) NOP(Continue Burst to END) ILLEGAL ILLEGAL*2 ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL NOP(Idle after tRP) NOP(Idle after tRP) NOP ILLEGAL*2 ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL NOP(Row Active after tRCD) NOP(Row Active after tRCD) NOP ILLEGAL*2 ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL NOP NOP NOP ILLEGAL*2 New Write, Determine AP. ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL WRITE with AUTO PRECHARGE L L L L L H L L L L L L L H L L L L L L L H L L L L L L L L PRECHARGING ROW ACTIVATING WRITE RECOVERING Doc # 14-02-045 Rev A ECN 01-1118 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. 27 NanoAmp Solutions, Inc. Table 15: Function Truth Table Current State /CS H L L L /RAS X H H H L L L L /CAS X H H L H H L L /WE X H L X H L H L X X X BA, CA, A8 BA, RA BA, A8 X Op-Code, Mode-Add Address Command DESEL NOP TERM READ/WRITE ACT PRE/PREA REFA MRS NT5DS4M32EG Advance Information Action NOP(Idle after tRP) NOP(Idel after tRP) NOP ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL REFRESHING L L L L ABBREVIATIONS : H=High Level, L=Low Level, V=Valid, X=Don't care BA=Bank Address, RA=Row Address, CA=Column Address, NOP=No Operation Note : 1. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle. 2. ILLEGAL to bank in specified state ; function may be legal in the bank indicated by BA, depending on the state of that bank. 3. Must satisfy bus contention, bus turn around, write recovery requirements. 4. NOP to bank precharging or in idle state, May precharge bank indicated by BA. 5. ILLEGAL if any bank is not idle. 6. Same bank's previous Auto precharge will not be performed. But if Bank is different, previous Auto precharge will be performed. ILLEGAL = Device operation and/or data-integrity are not guaranteed. Doc # 14-02-045 Rev A ECN 01-1118 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. 28 NanoAmp Solutions, Inc. NT5DS4M32EG Advance Information Table 16: Function Truth Table for CKE Current State CKEn-1 H L SELFREFRESHING L L L L L H L Both Bank Precharge POWER DOWN L L L L L H H H H ALL BANKS IDLE H H H H L H Any State Other than listed above H L L ABBREVIATIONS : H=High Level, L=Low Level, V=Valid, X=Don't care CKEn X H H H H H L X H H H H H L H L L L L L L L X H L H L /CS X H L L L L X X H L L L L X X H L L L L L L X X X X X /RAS X X H H H L X X X H H H L X X X H H H L L L X X X X X /CAS X X H H L X X X X H H L X X X X H H L H L L X X X X X /WE X X H L X X X X X H L X X X X X H L X H H L X X X X X Add X X X X X X X X X X X X X X X X X X X RA X Op Code X X X X X INVALID Action Exit Self-Refresh*1 Exit Self-Refresh*1 ILLEGAL ILLEGAL ILLEGAL NOP(Maintain Self-Refresh) INVALID Exit Power Down*2 Exit Power Down*2 ILLEGAL ILLEGAL ILLEGAL NOP(Maintain Power Down) Refer to Function True Table Enter Power Down*3 Enter Power Down*3 ILLEGAL ILLEGAL Row(& Bank) Active Enter Self-Refresh *3 Mode Register Access Refer to Current State=Power Down Refer to Function True Table Begin Clock Suspend next Cycle*4 Exit Clock Suspend next cycle*4 Maintain Clock Suspend Note : 1. After CKE's low to high transition to exist self refresh mode. And a time of tRC(min) has to be elapse after CKE's low to high transition to issue a new command. 2. CKE low to high transition is asynchronous as if restarts internal clock. A minimum setup time "tIS + one clock" must be satisfied before any command other than exit. 3. Power-down and self-refresh can be entered only from the all banks idle state. 4. Must be a legal command. Doc # 14-02-045 Rev A ECN 01-1118 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. 29 NanoAmp Solutions, Inc. NT5DS4M32EG Advance Information Timing Figure 24: Basic Timing (Setup, Hold and Access Time @BL=2, CL=3) COMMAND READA WRITEB WRITEC (A0~A7,A9~A11) (A0~A7,A9~A11) BA[1:0] BAa A8/AP ADDR ADDR /WE /WE /CAS /CAS /RAS DQS DQS CKE /CS /CK CK CK DQ Doc # 14-02-045 Rev A ECN 01-1118 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. DM Ca Ca 0 1 2 tRPRE tDQSQ Qa0 Qa1 3 tRPST tIS tIS tIH tIH BAb Cb Cb tWPRES tWPREH tWPREH tDS tDH tDS tDH tDS tDH tDS tDH tDQSS BAc Cc High High 4 5 6 tCH tCL tCK Db0 Db1 Dc0 Dc1 Hi-Z tDQSH tDQSL tWPST Hi-Z 7 8 30 NanoAmp Solutions, Inc. Figure 25: Multi Bank Interleaving READ (@BL=4, CL=3) COMMAND ACTIVEA ACTIVEB NT5DS4M32EG Advance Information (A0~A7,A9~A11) BA[1:0] A8/AP ADDR ADDR /RAS /CAS /WE CKE CKE /CS /CS /CK CK CK DM DQS DQ BAa Ra tRRD tRRD Rb Ra Rb 0 0 1 1 BAb 2 2 3 3 High 4 4 Doc # 14-02-045 Rev A ECN 01-1118 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. READA READA BAa Ca 5 5 6 6 READB READB Qa0 Qa1 Qa2 Qa3 Qb0 BAa Ca 7 7 8 8 9 9 10 10 31 NanoAmp Solutions, Inc. Figure 26: Multi Bank Interleaving WRITE (@BL=4, CL=3) (A0~A7,A9~A11) NT5DS4M32EG Advance Information Doc # 14-02-045 Rev A ECN 01-1118 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. COMMAND ACTIVEA BA[1:0] A8/AP ADDR ADDR /CAS /RAS /RAS /WE /WE CKE /CS /CK CK DQS DM tRCDW tRCDW DQ BAa BAa Ra Ra Ra 0 0 WRITEA ACTIVEB WRITEB tRRD tRRD BAa BAa Ca Ca 1 1 tDQSSmin tDQSSmin Da0 Da1 Da1 Da2 Da2 Da3 Da3 Db0 Db1 Db1 Db2 Db2 Db3 BAb BAb Rb Rb tRCDW tRCDW Cb Cb Rb 2 2 BAb BAb 3 HIGH HIGH 4 4 5 5 6 7 7 8 8 32 NanoAmp Solutions, Inc. Figure 27: Auto Precharge after READ Burst (@BL=8) DQS(CL=3) DQS(CL=3) (A0~A7,A9~A11) (A0~A7,A9~A11) NT5DS4M32EG Advance Information Doc # 14-02-045 Rev A ECN 01-1118 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. COMMAND COMMAND READA READA ACTIVEA DQ(CL=3) Qa0 Qa1 Qa2 Qa3 Qa4 Qa5 Qa6 Qa7 BA[1:0] ADDR A8/AP /CAS /CAS /RAS /WE CKE /CK CK CK DM DM /CS BAa Ca Ca 0 1 tRAS (min) 2 3 High 4 5 Auto precharge start tRP 6 *1 *1 BAa Ra Ra Ra 7 8 33 NanoAmp Solutions, Inc. Figure 28: Auto Precharge after WRITE Burst (@BL=4) COMMAND WRITEA Da0 Da1 Da1 Da2 Da2 Da3 Da3 ACTIVEA (A0~A7,A9~A11) (A0~A7,A9~A11) NT5DS4M32EG Advance Information BA[1:0] ADDR ADDR A8/AP /RAS /RAS /CAS DQS DQS /WE /WE CKE Doc # 14-02-045 Rev A ECN 01-1118 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. DM DQ tWPRES *1 /CS /CS /CK /CK CK BAa BAa 0 tWPREH tWPREH 1 2 3 tWR Auto precharge start Auto precharge start tRP tRP BAa Ra Ra High High 4 5 6 7 8 34 NanoAmp Solutions, Inc. Figure 29: Normal WRITE Burst (@BL=4) COMMAND WRITEA WRITEA Da0 Da1 Da1 Da2 Da3 Da3 PRECHARGE CHARGE NT5DS4M32EG Advance Information (A0~A7,A9~A11) BA[1:0] A8/AP ADDR ADDR /WE /CAS /CAS /RAS DQS CKE /CS /CK CK CK Doc # 14-02-045 Rev A ECN 01-1118 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. DM DQ tWPRES tWPRES 0 BAa Ca 1 tWPREH 2 3 High High 4 tWR BAa 5 6 7 8 35 NanoAmp Solutions, Inc. Figure 30: Write Interrupted by Precharge & DM (@BL=8) COMMAND WRITEA WRITEA Da0 Da1 Da2 Da3 tWR tWR Da4 Da5 PRECHARGE NT5DS4M32EG Advance Information (A0~A7,A9~A11) BA[1:0] ADDR ADDR A8/AP /CAS /RAS /RAS DQS /WE /WE CKE DM DM /CS DQ DQ tWPRES Da6 Da7 /CK CK CK BAa Ca 0 tWPREH 1 2 3 BAa High 4 WRITEB WRITEB tCCD tCCD WRITEC WRITEC Db0 Db1 Dc0 Dc1 Dc2 BAb Doc # 14-02-045 Rev A ECN 01-1118 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. Cc Cc 5 BAc 6 7 8 36 NanoAmp Solutions, Inc. Figure 31: Read Interrupted by Precharge (@BL=8) COMMAND READA PRE CHARGE NT5DS4M32EG Advance Information DQS(CL=3) DQ(CL=3) DQ(CL=3) (A0~A7,A9~A11) BA[1:0] A8/AP Doc # 14-02-045 Rev A ECN 01-1118 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. DM DM ADDR ADDR /CAS /RAS /RAS /WE CKE CKE /CK CK CK /CS 0 0 BAa Ca 1 1 2 2 3 3 BAa High 4 4 Qa0 Qa0 Qa1 Qa1 Qa2 Qa2 Qa3 Qa3 Qa4 Qa4 Qa5 Qa5 5 5 6 6 7 7 8 8 37 NanoAmp Solutions, Inc. NT5DS4M32EG Advance Information Figure 32: Read Interrupted by Burst stop & write (@BL=8, CL=3) (A0~A7,A9~A11) Doc # 14-02-045 Rev A ECN 01-1118 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. COMMAND READA Burst Stop BA[1:0] ADDR A8/AP /CAS /CAS /RAS /RAS /WE /WE CKE DQS /CK /CK CK /CS DM DQ DQ Qa0 Qa0 Qa1 Qa1 BAa Ca 0 0 1 1 2 2 3 3 High 4 4 WRITEB Db0 Db0 Db1 Db1 Db2 Db2 Db3 Db3 Db4 Qa5 Qa5 BAa Cb 5 5 6 6 7 7 8 8 38 NanoAmp Solutions, Inc. Figure 33: Read Interrupted by Read (@BL=8, CL=3) COMMAND READA tCCD READB Qa0 Qa1 Qb0 Qb1 Qb2 Qb3 Qb4 Qb5 Qb6 Qb7 (A0~A7,A9~A11) NT5DS4M32EG Advance Information BA[1:0] ADDR A8/AP /RAS /CAS /WE DQS CKE /CK CK /CS Doc # 14-02-045 Rev A ECN 01-1118 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. DM DQ BAa Ca BAb 0 BAb 1 2 3 High 4 5 6 7 8 39 NanoAmp Solutions, Inc. Figure 34: DM Function (@BL=8) only for write COMMAND WRITEA Da0 Da0 Command DQS DQ's Da5 DMM D Da6 tDS tDH tDS tDH Da1 /CK CK Da2 Da3 Da4 Da7 (A0~A7,A9~A11) NT5DS4M32EG Advance Information BA[1:0] A8/AP ADDR ADDR /CAS /RAS /RAS DQS /WE CKE /CK CK CK Doc # 14-02-045 Rev A ECN 01-1118 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. DM DM DQ DQ WRITE tWPRES /CS 0 BAa BAa Ca 1 1 tWPRES 0 tDQSS NOP tWPREH tWPREH tWPREH 2 8 1 2 3 4 5 6 7 3 NOP NOP NOP NOP NOP NOP NOP 4 4 High High Din 0 Din 1 Din 2 Din 3 Din 4 Din 5 Din 6 Din 7 5 Mask ed by DM=H 6 6 7 7 8 40 NT5DS4M32EG Advance Information /CK /CK CK CKE CKE /CS /RAS /RAS /CAS High 0 0 1 1 5 5 6 6 2 2 3 3 4 4 7 7 8 8 BA[1:0] BA[1:0] A8/AP ADDR (A0~A7,A9~A11) /WE /WE DQS DQS DQ DM High High High - Z High - Z tRP tMRD tMRD tRP tRFC tRFC tMRD Inputs must be stable for 200us Precharge Command All Bank All Bank EMRS Command MRS DLL Reset Command Precharge Command All Bank All Bank 1st Auto Refresh Command Command 2nd Auto Refresh Command Command Mode Register Set Command Minimum of 2 Refresh Cy cles are required Minimum of 2 Refresh Cy cles are required Any Command Command Doc # 14-02-045 Rev A ECN 01-1118 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. NanoAmp Solutions, Inc. Figure 35: Power Up Sequence & Auto Refresh (CBR) 41 NanoAmp Solutions, Inc. Figure 36: Mode Register Set (A0~A7,A9~A11) (A0~A7,A9~A11) NT5DS4M32EG Advance Information BA[1:0] A8/AP ADDR DQS DQS /WE /CAS /RAS DM High High DQ High - Z CKE /CK CK CK /CS /CS High - Z 0 Doc # 14-02-045 Rev A ECN 01-1118 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. Precharge All Bank Command 1 2 tRP tRP 3 Mode Register Set Command 4 High High tMRD 5 Any Command Command 6 7 8 42 NanoAmp Solutions, Inc. NT5DS4M32EG Advance Information IBIS : I/V CHARACTERISTICS FOR INPUT AND OUTPUT BUFFERS Reduced Output Driver Characteristics. 1. The nominal pulldown V-I curve for DDR SDRAM devices will be within the inner bounding lines of the V-I curve of below figure. 2. The full variation in driver pulldown current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of below figure 80.0 70.0 60.0 50.0 Maximum Typical High Typical Low Minimum Iout (mA) 40.0 30.0 20.0 10.0 0.0 0.1 0.6 1.1 1.6 2.1 Vout (V) 3. The nominal pullup V-I curve for DDR SDRAM devices will be within the inner bounding lines of the V-I curve of below figure. 4. The full variation in driver pullup current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of below figure 0.0 -10.0 -20.0 -30.0 -40.0 -50.0 -60.0 -70.0 -80.0 -90.0 -100.0 -110.0 0.1 0.6 1.1 1.6 2.1 Minimum Typical Low Iout (mA) Typical High Maximum Vout (V) 5. The full variation in the ratio of the maximum to minimum pullup and pulldown current will not exceed 1.7, for device drain to source voltage from 0 to VDDQ/2 6. The full variation in the ratio of the nominal pullup to pulldown current should be unity 0%, for device drain to source voltages from 0 to VDDQ/2 Doc # 14-02-045 Rev A ECN 01-1118 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. 43 NanoAmp Solutions, Inc. NT5DS4M32EG Advance Information Table 17: Pulldown and Pullup IV Characteristics Voltage (V) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 Pulldown Current(mA) Typical Low 3.3 6.6 9.8 13.0 16.1 18.7 21.3 23.6 25.6 27.7 29.2 30.3 31.3 32.0 32.5 32.7 32.9 33.2 33.5 33.8 33.9 34.2 34.5 34.6 34.9 Typical High 3.7 7.3 10.9 14.4 17.8 21.1 23.9 26.9 29.8 32.6 35.2 37.7 40.1 42.4 44.4 46.4 48.1 49.8 51.5 52.5 53.5 54.5 55.0 55.5 56.0 Min 2.5 5.0 7.4 10.0 12.4 14.9 17.4 19.9 21.4 23.0 24.2 25.0 25.4 25.6 25.8 25.9 26.2 26.4 26.5 26.7 26.8 26.9 27.0 27.0 27.1 Max 4.8 9.4 14.0 18.3 22.6 26.7 30.7 34.1 37.7 41.2 44.5 47.7 50.7 53.5 56.0 58.6 60.6 62.6 64.6 66.6 68.3 69.9 71.5 72.9 74.1 Typical Low -3.3 -6.6 -9.8 -12.9 -16.1 -18.5 -20.5 -22.2 -23.6 -24.8 -25.8 -26.6 -27.0 -27.2 -27.4 -27.5 -27.6 -27.7 -27.8 -27.9 -28.0 -28.1 -28.2 -28.2 -28.3 Pullup Current(mA) Typical High -4.1 -7.8 -11.4 -14.9 -18.4 -21.9 -25.3 -28.7 -32.1 -35.4 -38.6 -41.9 45.2 -48.4 -51.6 -54.7 -57.8 -60.7 -64.1 -67.0 -69.8 -72.7 -75.6 -78.4 -81.3 Min -2.5 -5.0 -7.4 -10.0 -12.4 -14.9 -17.4 -19.5 20.6 -20.9 -21.1 -21.2 -21.3 -21.4 -21.5 -21.6 -21.7 -21.8 -21.8 -21.9 -21.9 -22.0 -22.0 -22.1 -22.2 Max -4.9 -9.7 -14.5 -19.2 -23.9 -28.4 -32.9 -37.3 -41.7 -46.0 -50.7 -54.3 -58.4 -62.4 -66.4 -70.4 -73.8 -77.8 -81.3 -84.7 -88.1 -91.6 -95.0 -97.0 -101.3 Temperature (Ambient) Typical 25 C Minimum70C Maximum 0C Vdd/Vddq Typical 2.50V / 2.50V Minimum 2.375V / 2.375V Maximum2.625V / 2.625V The above characteristics are specified under best, worst and normal process variation/conditions Doc # 14-02-045 Rev A ECN 01-1118 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. 44 NanoAmp Solutions, Inc. Figure 37: Package Dimensions (144-Balls FBGA) A1 INDEX MARK NT5DS4M32EG Advance Information 12.0 12.0 0.80x11=8.8 0.10 MAX 0.80 A B C 0.80 0.45 0.05 D E F G H J K L M 12 11 10 9 87 654 321 0.80x11=8.8 0.40 0.35 0.05 1.40 Max 0.40 < Bottom View > Doc # 14-02-045 Rev A ECN 01-1118 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. 45 NanoAmp Solutions, Inc. NT5DS4M32EG Advance Information Revision History Revision A Date March 2005 Initial Release Change Description (c) 2005 Nanoamp Solutions, Inc. All rights reserved. NanoAmp Solutions, Inc. ("NanoAmp") reserves the right to change or modify the information contained in this data sheet and the products described therein, without prior notice. NanoAmp does not convey any license under its patent rights nor the rights of others. Charts, drawings and schedules contained in this data sheet are provided for illustration purposes only and they vary depending upon specific applications. NanoAmp makes no warranty or guarantee regarding suitability of these products for any particular purpose, nor does NanoAmp assume any liability arising out of the application or use of any product or circuit described herein. NanoAmp does not authorize use of its products as critical components in any application in which the failure of the NanoAmp product may be expected to result in significant injury or death, including life support systems and critical medical instrument. Doc # 14-02-045 Rev A ECN 01-1118 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. 46 |
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